A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor. The 64-point FFT is realized by decomposing it into a 2-D structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use any 2-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25 ?m BiCMOS technology. The core area of this chip is 6.8 mm2. The average dynamic power consumption is 41 mW @ 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i. e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption

New virtually scaling free adaptive CORDIC rotator

In this article we propose a novel CORDIC rotator algorithm that eliminates the problems of scale factor compensation and limited range of convergence associated with the classical CORDIC algorithm. In our scheme, depending on the target angle or the initial coordinate of the vector, a scaling by 1 or 1/?2 is needed that can be realised with minimal hardware. The proposed CORDIC rotator adaptively selects appropriate iteration steps and converges to the final result by executing 50% less number of iterations on an average compared to that required for the classical CORDIC. Unlike classical CORDIC, the final value of the scale factor is completely independent of number of executed iterations. Based on the proposed algorithm, a 16-bit pipelined CORDIC rotator implementation has been described. The silicon area of the fabricated pipelined CORDIC rotator core is 2.73 mm2. This is equivalent to 38 k inverter gates in IHP in-house 0.25 ?m BiCMOS technology. The average dynamic power consumption of the fabricated CORDIC rotator is 17 mW @ 2.5 V supply and 20Msps throughput. Currently, this CORDIC rotator is used as a part of the baseband processor for a project that aims to design a single-chip wireless modem compliant with IEEE 802.11a and Hiperlan/2

A CORDIC like processor for computation of arctangent and absolute magnitude of a vector

In this paper, we propose a CORDIC like algorithm for computing absolute magnitude of a vector and its corresponding phase angle. It eliminates scale factor compensation step as well as the addition/subtraction operation along the z datapath. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications

Baseband processor for IEEE 802.11a standard with embedded BIST

In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported

A 16-bit CORDIC rotator for high-performance wireless LAN

In this paper we propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm2 and it dissipates 7 mW power at 20 MHz frequency

OFDM synchronizer implementation for an IEEE 802.11(a) compliant modem

In OFDM transmissions, synchronization arises to be one of the most critical operations. The reason for that is the preservation of orthogonality: timing offsets and frequency offsets destroy easily this orthogonality, leading to Inter-Symbol Interference (ISI) as well as Inter-Carrier Interference (ICI). This paper is focused on the implementation of a synchronizer for the IEEE 802.11a standard, which is based on the OFDM transmission scheme. Furthermore, during this year the first chips compliant with the standard are to be deployed, for that reason we also present a comparison of our solution, which is based on the one presented in with two other ones proposed

A Low-Power 64-point FFT/IFFT Architecture for Wireless Broadband Communication

A low power 64-point FFT/IFFT architecture is developed for the application in OFDM based wireless broadband communication system. The proposed architecture satisfies the specifications of IEEE 802.11a and ETSI Bran. The architecture requires 25% multiplication and 86% addition/subtraction operation compared to the conventional Cooley-Tukey approach. This leads to power and area saving as well. The architecture is capable to perform FFT and IFFT without changing the internal coefficients which makes it highly suitable for practical applications

A novel 64-point FFT/IFFT processor for IEEE 802.11(a) standard

A novel 64-point FFT/IFFT processor is presented in this article, named TURBO64, developed primarily for the application for the IEEE 802.11(a) standard. The processor does not use any digital multiplier or RAM. It has been fabricated and tested successfully. Its core area is 6.8 mm2 and the average power consumption is 41 mW at 1.8 V @ 20 MHz frequency. Compared to some other existing IP cores and ASIC chips TURBO64 needs a smaller number of clock cycles and consumes less power

Low Complexity Radar Gesture Recognition Using Synthetic Training Data

Developments in radio detection and ranging (radar) technology have made hand gesture recognition feasible. In heat map-based gesture recognition, feature images have a large size and require complex neural networks to extract information. Machine learning methods typically require large amounts of data and collecting hand gestures with radar is time- and energy-consuming. Therefore, a low computational complexity algorithm for hand gesture recognition based on a frequency-modulated continuous-wave (FMCW) radar and a synthetic hand gesture feature generator are proposed. In the low computational complexity algorithm, two-dimensional Fast Fourier Transform is implemented on the radar raw data to generate a range-Doppler matrix. After that, background modelling is applied to separate the dynamic object and the static background. Then a bin with the highest magnitude in the range-Doppler matrix is selected to locate the target and obtain its range and velocity. The bins at this location along the dimension of the antenna can be utilised to calculate the angle of the target using Fourier beam steering. In the synthetic generator, the Blender software is used to generate different hand gestures and trajectories and then the range, velocity and angle of targets are extracted directly from the trajectory. The experimental results demonstrate that the average recognition accuracy of the model on the test set can reach 89.13% when the synthetic data are used as the training set and the real data are used as the test set. This indicates that the generation of synthetic data can make a meaningful contribution in the pre-training phase